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Tenstorrent
Dft Engineer
Austin, Texas, United States · Hybrid · Full time · Mid level
$100k–$500k / year
About the role
Design for Test (DFT) engineer for high-performance AI/ML chip designs. Involved in RTL to tapeout implementation for multiple IPs, focusing on test cost reduction and high coverage.
What you’ll do
• Implement and integrate DFT features into RTL. • Own ATPG and test coverage analysis. • Plan and verify MBIST with Test Engineering. • Develop and refine DFx flows and methodology.
What you’ll bring
• BS/MS/PhD in EE/ECE/CE/CS with 5+ years industry experience. • Fluent in Verilog RTL and SystemVerilog/UVM. • Experience with ATPG, DFx tools, fault models, low-power flows. • Strong debug and collaboration skills. • Eligible to access U.S. export-controlled technology.
Life at Tenstorrent
Highly competitive compensation and benefits. Equal opportunity employer.
About Tenstorrent
Tenstorrent leads in cutting-edge AI technology, developing high performance RISC-V CPUs and AI platforms.