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Neuralink
Physical Design and Verification Engineer
South San Francisco, California, United States · On-site · Full time · Senior level
$131k–$265k / year
About the role
Lead block-to-full-chip implementation and signoff on advanced-node, multi-die 3DIC products. Drive hierarchical physical design and multi-physics verification for stacked-die systems.
What you’ll do
• Define and execute hierarchical partitioning strategy. • Develop and maintain floorplans and timing budgets. • Manage die-to-die partitioning for 3D stacks. • Drive logic synthesis and RTL-to-gate correlation. • Perform multi-physics verification including thermal and mechanical analysis.
What you’ll bring
• BS/MS in Electrical/Computer Engineering with 5+ years experience. • Proven RTL-to-GDSII experience on advanced nodes. • Strong command of STA and physical verification signoff. • Proficiency with PnR and signoff tools and TCL scripting. • Work authorization for United States.
Life at Neuralink
Offers medical, dental, vision insurance, paid holidays, commuter benefits, meals, equity, 401(k), parental leave, and flexible time off.
About Neuralink
Neuralink creates devices enabling bi-directional brain interfaces to restore movement, sight, and revolutionize human-digital interaction.